Dynamic random access semiconductor memories (DRAMs) contain a matrix of memory cells which are connected up in the form of rows via word lines and columns via bit lines. Data are read from the memory cells or data are written to the memory cells as a result of activation of suitable word and bit lines. A dynamic memory cell generally comprises a selection transistor and a storage capacitor, the selection transistor normally being in the form of a horizontally designed field effect transistor and comprising two diffusion regions which are isolated by a channel above which there is a gate which is connected to a word line. One of the diffusion regions of the selection transistor is connected to a bit line, and the other diffusion region is connected to the storage capacitor. Applying a suitable voltage to the gate via the word line turns on the selection transistor and permits a flow of current between the diffusion regions in order to charge the storage capacitor via the bit line.
The continual striving to reduce the size of DRAM memory chips has resulted in the design of DRAM memory cells in which the storage capacitor, in particular, uses the third dimension. Fundamental embodiments of three-dimensional storage capacitors which have been developed are trench capacitors and stack capacitors, with the trench capacitor type normally being used in DRAM memory cells. The trench capacitor comprises a trench which is etched into the semiconductor substrate and is filled with a highly conductive material which serves as an internal capacitor electrode. By contrast, the external capacitor electrode is buried in the substrate and is isolated from the internal capacitor electrode by a dielectric layer. The electrical connection between the diffusion region of the selection transistor and the first internal capacitor electrode is generally made in the upper trench region by a capacitor connection, which is normally in the form of a diffusion region and is called the buried strap.
To produce DRAM memory cell arrays having a memory cell comprising a planar selection transistor and a trench capacitor, use is normally made of process technologies in which the electrical junction is independent of the orientation of the diffusion regions of the selection transistors and the trench capacitors with respect to one another. In this production method, the active regions, i.e. the diffusion regions, of the selection transistor are arranged in rows in a first direction and the trench capacitors are arranged in rows in a second direction, which runs transversely with respect to the first direction, the conductive junctions between the active regions of the selection transistors and the trench capacitors on the overlapping areas of the rows which run at right angles to one another being respectively produced in both edge regions of the overlapping area in the first direction.
This double-sided buried-strap cell array concept is increasingly being replaced by the single-sided buried-strap concept, however, which can be used to produce cell array geometries which are easier to map lithographically. In the case of this cell array technology, the conductive junctions between the active regions of the selection transistors and the trench capacitors on the overlapping areas of the rows (running at right angles to one another) of active regions of the selection transistors in a first direction and trench capacitors in a second direction are respectively produced only in a single edge region in the first direction of the overlapping area in the first direction. By contrast, in the opposite edge region, the active region of the selection transistor is insulated from the underlying trench capacitor. This single-sided buried-strap cell array concept allows a checkerboard cell geometry to be produced, in particular, in which the memory cells at the crossover points between the active regions of the selection transistors and the trench capacitors in adjacent rows are arranged offset from one another.
DRAMs are normally produced in large numbers at the same time on a semiconductor plate, the wafer. When the DRAM memories are finished, they are split up by cracking and breaking or sawing at interspaces, kerfs, provided for this purpose. The semiconductor pieces with the individual DRAM memories, the DRAM chips, are then incorporated into a package and are electrically conductively connected to contact lugs.
Before the wafers are split into the individual chips, function tests for the individual DRAM memory cells are generally performed at wafer level. These function tests are intended to indicate the general operation of the memory cells. This also allows the electrical properties of the DRAM memory cells and hence particularly of the selection transistors to be characterized. At the same time, function tests are also performed on memory cells in which it is possible to vary important parameters, particularly of the selection transistors, in order to establish possible tolerances in the memory cell. In this case, the necessary measurements for the function tests are normally not performed on the memory cells themselves, but rather on special test structures which are produced together with the DRAM memory cells on the wafer, in order to ensure that the test structures indicate the operability or the electrical properties of the actual DRAM memory cells. The test structures are normally produced in space-saving fashion between the DRAM memories in the kerfs, that is to say the regions which are later used to split the wafer into the individual chips.
To test the test structures, automatic testers are generally used. These testers normally have an arrangement of test needles with 25 measuring tips arranged in a row which are used for simultaneously making contact with a corresponding number of contact areas on the test structures. Using the automatic testers, currents and voltages are applied to the test structure, and the electrical properties of the test components arranged between the contact areas are measured and evaluated in order to obtain statements about the quality of the production process for the DRAM memory cells on the wafer.
For the double-sided buried-strap DRAM memory cell concept, test structures for measuring the electrical properties of the individual DRAM memory cells and, at the same time, particularly the parameters of the selection transistors are already known. For the single-sided buried-strap cell concepts, on the other hand, the prior art has not yet developed any test structures for the individual DRAM memory cells, particularly the selection transistors, which can be used to ascertain the electrical properties of the DRAM elementary cells easily and accurately.
U.S. Pat. No. 6,339,228 D1 has disclosed test structures for a single-sided buried-strap DRAM memory cell array (Note: term is recorded in paragraph 1 on page 2 of the decision).